Introduction – JK Flip-Flop
A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR type is defined in the JK type. If you remember, sometimes are outputs on the SR flip-fop looked all screwy; this was because it was in an indeterminate state.
Inputs J and K behave like inputs S and R to set and clear the flip-flop (note that in a JK flip-flop, the letter J is for set and the letter K is for clear). When logic 1 inputs are applied to both J and K simultaneously, the flip-flop switches to its complement state, ie., if Q=1, it switches to Q=0 and vice versa. In that way it is like a toggle.
A clocked JK flip-flop is shown below. Output Q is ANDed with K and CP inputs so that the flip-flop is cleared during a clock pulse only if Q was previously 1. Similarly, ouput Q’ is ANDed with J and CP inputs so that the flip-flop is set with a clock pulse only if Q’ was previously 1.
Note that because of the feedback connection in the JK flip-flop, a CP signal which remains a 1 (while J=K=1) after the outputs have been complemented once will cause repeated and continuous transitions of the outputs. To avoid this, the clock pulses must have a time duration less than the propagation delay through the flip-flop. The restriction on the pulse width can be eliminated with a master-slave or edge-triggered construction. The same reasoning also applies to the T flip-flop presented next.
Figure 6
T Flip-Flop
The T flip flop is really just a single input jk flip flop. To make one, we just have to hook up the wires to a single input.
Source: http://wearcam.org/ece385/lectureflipflops/flipflops/
